Computer systems (e.g., integrated microcomputers) comprise processors (e.g., a central processing unit CPU), memory units (e.g., a random access memory RAM), busses, and other components. Interfaces exchange data and control information between these components and peripheral devices (e.g., displays, printers, buzzers). For example, the processor writes data to the memory and the interface sends this data to the peripheral device, or vice versa. To save processor resources, it is convenient to control the interfaces partly or completely independent from the processor. For example, the interface can receive control signals (so-called "triggers") from, e.g., a timer.
When a first trigger arrives, the interface transfers a predetermined data set, a so-called "queue". However, a second trigger arriving while the interface is busy could lead to a trigger collision. To avoid collisions, consecutive triggers should arrive with a certain delay. Appropriate software in the timer can satisfy this requirement. But such an approach is cost intensive and can lead to errors.
The interface can store a trigger collision bit (TCB) for each queue Q(i) in a register. Such a TCB can be asserted by an incoming trigger signal T(i) and negated after the queue transfer is completed. The interface does not receive any new arriving trigger signals as long as TCB is asserted. But this approach is also not wanted, because some trigger signals might get lost without having invoked a queue transfer.
A queued serial peripheral interface unit (QSPI) is incorporated in many microcomputers and peripherals designed. The following references are useful: U.S. Pat. No. 4,816,996 (hereinafter "reference '996") and U.S. Pat. No. 4,958,277 (hereinafter "reference '277") both to Hill et al., and "Queued Serial Module (QSM) Reference Manual" by Motorola, Inc. 1991, order number QSMRM/AD.
The present invention seeks to provide a computer system with an improved interface which mitigates or avoids these and other disadvantages and limitations of the prior art.